Mask layout and method for forming vertical channel transistor in semiconductor device using the same

Abstract

A method for forming a vertical channel transistor in a semiconductor memory device includes: forming a plurality of pillars over a substrate so that the plurality of pillars are arranged in a first direction and a second direction crossing the first direction, and so that each of the pillars has a hard mask pattern thereon; forming an insulation layer to fill a regions between the pillars; forming a mask pattern over a resultant structure including the insulation layer, wherein the mask pattern has openings exposing gaps between each two adjacent pillars in the first direction; etching the insulation layer to a predetermined depth using the mask pattern as an etching barrier to form trenches; and filling the trenches with a conductive material to form word lines extending in the first direction.

Dependencies are inferred from the claim text.