Integrated circuit interconnect structure

A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• an integrated circuit (IC) interconnect including:
• a first via positioned in a dielectric and coupled to a high current device at one end;
• a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof and the buffer metal segment comprising a plurality of electrically insulating inter-dielectric (ILD) pads forming a ILD cheesing pattern thereon, to direct current;
• a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end;
• and
• a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof.

A method comprising:

• forming a high current device;
• forming a first via positioned in a dielectric and coupled to the high current device at one end;
• forming a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof
• forming a plurality of electrically insulating inter-dielectric (ILD) pads forming a ILD cheesing pattern on the buffer metal segment, to direct current;
• forming a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end;
• and
• forming a metal power line in a dielectric and coupled to the second via at an opposite end thereof.