Layout Testing Method and Wafer Manufacturing Method
AssigneeSamsung Electronics Co., Ltd.
InventorsDaewook Kim, Yong Hee Park, Ji-Seong Doh
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AssigneeSamsung Electronics Co., Ltd.
InventorsDaewook Kim, Yong Hee Park, Ji-Seong Doh
Estimating the term…
A product layout testing method includes testing and correcting one or more patterns of a product layout, detecting and correcting electrical characteristic changes of transistors of the product layout, and testing whether a product characteristic predicted from the product layout is equal to that predicted from a designed circuit view. Weak points with respect to the pattern may be detected and corrected, electrical characteristic changes depending on layout parameters may be detected and corrected, and whether a circuit operation depending on parasitic components is normal may be checked.
A layout testing method comprising:
A wafer manufacturing method comprising:
A layout testing method comprising:
Dependencies are inferred from the claim text.