Body tie test structure for accurate body effect measurement
AssigneeGlobalfoundries Inc.
InventorsSriram MADHAVAN, Qiang CHEN, Darin A. CHAN, Jung-Suk GOO
Life of this patent
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Abstract
A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.
Claims17
A method of fabricating a semiconductor device, the method comprising:
- providing a layer of semiconductor material;
- forming a cross-shaped gate structure over the layer of semiconductor material, the cross-shaped gate structure having a first cross bar oriented in a first direction and a second cross bar oriented in a second direction, the cross-shaped gate structure having a substantially constant gate length L, and the cross-shaped gate structure corresponding to a cross-shaped body region in the semiconductor material underlying the cross-shaped gate structure;
- halo implanting a dopant in the cross-shaped body region;
- forming a blocking layer over the layer of semiconductor material and over the cross-shaped gate structure to block ion implantation and salicide formation on material located under the blocking layer;
- forming source and drain regions in the layer of semiconductor material;
- and
- forming a body tie region in the layer of semiconductor material, the body tie region separated from the source and drain regions by the layer of semiconductor material underlying the blocking layer.
A method of fabricating a semiconductor based body tie test device, the method comprising:
- forming a cross-shaped body region in a layer of semiconductor material, the cross-shaped body region comprising an intrinsic body region characterized by a channel length L, and further comprising an extrinsic body region characterized by the channel length L;
- forming source and drain regions in the layer of semiconductor material, the intrinsic body region separating the source region from the drain region;
- forming a spacer region in the layer of semiconductor material, the extrinsic body region separating the source and drain regions from the spacer region;
- and
- forming a body tie region in the layer of semiconductor material, the spacer region separating the body tie region from the source and drain regions.
A method of fabricating a semiconductor based body tie test device, the method comprising:
- forming a cross-shaped gate structure over a layer of semiconductor material, the cross-shaped gate structure comprising a first cross bar and a second cross bar perpendicular to the first cross bar, the cross-shaped gate structure having a substantially constant gate length L;
- halo implanting a dopant in a cross-shaped body region underlying the cross-shaped gate structure, the cross-shaped body region comprising an intrinsic body region and an extrinsic body region;
- forming source and drain regions by ion implantation in the layer of semiconductor material, the intrinsic body region separating the source region from the drain region;
- forming a body tie region by ion implantation in the layer of semiconductor material, wherein a spacer region separates the body tie region from the source and drain regions.
Dependencies are inferred from the claim text.