US 2010/0304537 A1 · Semiconductor Devices Including a Topmost Metal Layer with at Least one Opening and Their Methods of Fabrication

Abstract

In one embodiment, a semiconductor device has a topmost or highest conductive layer with at least one opening. The semiconductor device includes a semiconductor substrate having a cell array region and an interlayer insulating layer covering the substrate having the cell array region. The topmost conductive layer is disposed on the interlayer insulating layer in the cell array region. The topmost conductive layer has at least one opening. A method of fabricating the semiconductor device is also provided. The openings penetrating the topmost metal layer help hydrogen atoms reach the interfaces of gate insulating layers of cell MOS transistors and/or peripheral MOS transistors during a metal alloy process, thereby improve a performance (production yield and/or refresh characteristics) of a memory device.

Claims21

Dependent claims

A method of fabricating a semiconductor device comprising:

preparing a semiconductor substrate having a cell array region;
forming an interlayer insulating layer covering the semiconductor substrate;
and
forming a topmost conductive layer having at least one opening on the interlayer insulating layer in the cell array region.

1 more element

A method of fabricating a semiconductor device, the method comprising:

providing a semiconductor substrate having a cell array region and a peripheral circuit region;
forming a plurality of memory cells and at least one peripheral MOS transistor on the semiconductor substrate in the cell array region and on the semiconductor substrate in the peripheral circuit region, respectively;
forming an interlayer insulating layer over the memory cells and the peripheral MOS transistor;
and
forming a first topmost metal layer and a second topmost metal layer on the interlayer insulating layer in the cell array region and on the interlayer insulating layer in the peripheral circuit region respectively,
wherein the first topmost metal layer is formed to have at least one first opening over the cell array region and the second topmost metal layer is formed to have at least one second opening over the peripheral MOS transistor.

3 more elements

Dependencies are inferred from the claim text.

Semiconductor Devices Including a Topmost Metal Layer with at Least one Opening and Their Methods of Fabrication

Life of this patent

Semiconductor Devices Including a Topmost Metal Layer with at Least one Opening and Their Methods of Fabrication

Life of this patent

Abstract

Claims21