Method for insulating wires of semiconductor device

A method for insulating wires of a semiconductor device, the method comprising:

• forming first bit line stacks over a cell region of a semiconductor substrate and second bit line stacks over a peripheral region of the semiconductor substrate;
• forming a spacer layer to cover the first and second bit line stacks;
• forming a first mask that selectively exposes a portion of the spacer layer placed over the cell region;
• etching the exposed portion of the spacer layer to leave the other portion of the spacer layer present on the peripheral region as an etch stop layer and selectively attach a spacer to a side wall of the first bit line stack;
• forming a first insulation layer of a flowable insulation material that fills between the first and second bit line stacks;
• etching back the first insulation layer to expose upper side portions of the first and second bit line stacks;
• selectively removing a portion of the first insulation layer present on the peripheral region;
• and
• forming a second insulation layer denser than the first insulation layer to cover a portion of the first insulation layer present on the cell region, and to fill the second bit line stacks present on the peripheral region.

A method for insulating wires of a semiconductor device, the method comprising:

• forming a lower insulation layer;
• sequentially depositing over the lower insulation layer a bit line conductive layer and a capping layer;
• patterning the bit line conductive layer and the capping layer to form first and second bit line stacks, wherein the first bit line stacks has Critical Dimension (CD) and space less than that of the second bit line stacks;
• forming a spacer layer to cover the first and second bit line stacks;
• selectively etching a portion of a spacer layer covering the first bit line stacks to leave the other portion of the spacer layer covering the second bit line stacks as an etch stop layer, and selectively attach a spacer to a side wall of the first bit line stack;
• forming a SOD layer to fill between the first and second bit line stacks;
• etching back the SOD layer to expose upper side portions of the first and second bit line stacks;
• selectively etching the portion of the SOD layer present between the second bit line stacks to expose the etch stop layer;
• depositing a HDP insulation layer to cover the unetched portion of the SOD layer and to fill between the second bit line stacks;
• forming a metal contact that penetrates the HDP insulation layer to be aligned with the second bit line stack;
• and
• forming a metal wire that is electrically connected to the metal contact.