Partitioning features of a single ic layer onto multiple photolithographic masks

A set of photolithography masks used to manufacture an integrated circuit, comprising:

• a first mask having a first set of alignment marks and adapted to pattern an integrated circuit (IC) layer, the first mask comprising a first series of longitudinal segments extending in parallel with one another along a first direction, where neighboring longitudinal segments of the first series are separated by a first distance;
• and
• a second mask having a second set of alignment marks and adapted to pattern the IC layer, the second mask comprising a second series of longitudinal segments extending in parallel with one another along the first direction, where neighboring longitudinal segments of the second series are separated by a second distance;
• wherein when the second mask overlies the first mask so the first and second sets of alignment marks are aligned, a longitudinal segment of the second series is spaced between a pair of neighboring longitudinal segments of the first series.

A method for processing an integrated circuit (IC) layer, comprising:

• generating a first physical mask for patterning the IC layer, the first physical mask comprising:
• a first series of longitudinal segments extending in parallel with one another along a first direction, and a first portion of a coupling segment extending in a second direction and coupled to a longitudinal segment in the first series;
• generating a second physical mask for patterning the IC layer, the second physical mask comprising:
• a second series of longitudinal segments extending in parallel with one another along the first direction, and a second portion of the coupling segment coupled to a longitudinal segment in the second series, the second series having fewer than all of the longitudinal segments in the IC layer and differing from the first series.