Feature-quantity extracting method, designed-circuit-pattern verifying method, and computer program product

A designed-circuit pattern verifying method comprising:

• setting feature-quantity extraction parameters used by feature-quantity extraction functions for calculating feature quantities used as explanatory variables of a resist model for predicting a resist image;
• causing the feature-quantity extraction functions, for which the feature-quantity extraction parameters are set, to act on optical images of a circuit pattern created by a designer and calculating feature quantities at a plurality of points of the circuit pattern from the optical images;
• comparing a distribution of the calculated feature quantities and a distribution of feature quantities of test patterns and extracting a point of the circuit pattern deviating from a range of the feature quantity distribution of the test patterns;
• and
• displaying the extracted point of the circuit pattern on a display device.