Parametric Testline with Increased Test Pattern Areas

An integrated circuit parametric testline comprising:

• a substrate;
• a dielectric layer formed atop said substrate;
• a first probe pad formed on said dielectric layer;
• and
• a first stacking via structure formed under and coupled to said first probe pad,
• wherein said first stacking via structure comprises a metal layer having an edge not parallel to the edges of said parametric testline.

A testline structure comprising:

• a first probe pad on a top surface of a dielectric layer;
• a first stacking structure under said top surface of said dielectric layer and coupled to said first probe pad;
• and
• a first device under test (DUT) coupled to said first stacking structure, wherein a first portion of said first DUT directly underlies a first area of said top surface of said dielectric layer, wherein said first area is defined by an edge of said first probe pad, a longitudinal edge of said testline structure, and a first line perpendicular to said longitudinal edge.

A testline structure comprising:

• a first probe pad on a top surface of a dielectric layer;
• a second probe pad on said top surface of said dielectric layer;
• a first stacking structure under said top surface of said dielectric layer and coupled to said first probe pad;
• a second stacking structure under said top surface of said dielectric layer and coupled to said second probe pad;
• and
• a first device under test (DUT) coupled to said first stacking structure and said second stacking structure, wherein a first portion of said first DUT is outside of an area parallel to said top surface of said dielectric layer and defined by longitudinal boundaries of said testline structure and boundaries perpendicular to said longitudinal boundaries, wherein said boundaries perpendicular to said longitudinal boundaries each intersect a point on one of said first stacking structure and said second stacking structure, and wherein a second portion of said first DUT is inside said area.