Semiconductor structures for biasing devices
AssigneeWolfson Microelectronics plc
InventorJOHN LAURENCE PENNOCK
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Abstract
Semiconductor structures with high impedances for use in biasing for applying voltage bias to part of a device. The semiconductor structure comprises a continuous structure having a plurality of regions of a first semiconductor type (n type or p type) material arranged alternately with at least one region of the opposite type. The structure may be formed from polysilicon and may also include a plurality of intrinsic regions arranged between the n and p type regions. The structure forms a composite diode and provides a high impedance.
Claims48
A device comprising a MEMS transducer and a biasing means for applying a voltage bias to said MEMS transducer wherein the biasing means comprises a semiconductor structure comprising:
- a continuous structure of semiconducting material comprising a plurality of regions of first semiconductor type, being n type or p type, and a plurality of regions of a second semiconductor type, being n type or p type and the opposite type to the first type, the regions of first semiconductor type and second semiconductor type being arranged alternately.
A high impedance device comprising a semiconductor structure, said semiconductor structure comprising a continuous structure of semiconducting material comprising a plurality of regions of first semiconductor type, being n type or p type, and a plurality of regions of a second semiconductor type, being n type or p type and the opposite type to the first type, the regions of first semiconductor type and second semiconductor type being arranged alternately.
A method of biasing a MEMS transducer comprising the steps of arranging a high impedance element between the MEMS transducer and a reference voltage level wherein said high impedance element comprises a semiconductor structure comprising:
- a continuous structure of semiconducting material comprising a plurality of regions of first semiconductor type, being n type or p type, and a plurality of regions of a second semiconductor type, being n type or p type and the opposite type to the first type, the regions of first semiconductor type and second semiconductor type being arranged alternately.
A method of fabricating a high impedance device comprising the steps of:
- depositing a layer of semiconductor material onto a substrate;
- and
- forming, in said layer of semiconductor material, a plurality of regions of a first semiconductor type, being n-type or p-type, and also forming at a plurality of regions of a second semiconductor type, being n-type or p-type and of opposite type to the first semiconductor regions, said first and second regions being arranged alternately.
Dependencies are inferred from the claim text.