Semiconductor device and method of manufacturing the same
AssigneeDongbu HiTek Co., Ltd.
InventorYeo-Cho Yoon
Life of this patent
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Abstract
A semiconductor device includes a semiconductor substrate including a CMOS region and a bipolar region, a first N well and a first P well in the CMOS region, a PMOS device in the first N well and an NMOS device in the first P well, a deep P well in the bipolar region, a second N well in the deep P, a second isolation layer between the deep P well and the second N well, a third isolation in the second N well, a collector in the second N well between the second and third isolation layers, and a base formed in the second N well and having a bottom surface including first type impurities to contact the emitter.
Claims20
An apparatus comprising:
- a semiconductor substrate including a CMOS region and a bipolar region;
- a first N well and a first P well formed in the CMOS region and separated from each other by a first isolation layer;
- a PMOS device formed in the first N well and an NMOS device formed in the first P well;
- a deep P well formed in the bipolar region;
- a second N well formed in the deep P well to expose a portion of the deep P well;
- a second isolation layer formed between the deep P well and the second N well to define an emitter region;
- an emitter having second type impurities formed in the deep P well;
- a third isolation layer defining base and collector regions formed in the second N well;
- a collector having second type impurities formed in the second N well between the second and third isolation layers;
- and
- a base formed having first type impurities formed in the second N well at one side of the third isolation layer and having a bottom surface which contacts the emitter.
A method comprising:
- forming a semiconductor substrate including a CMOS region and a bipolar region;
- forming a first isolation layer in the CMOS region and second and third isolation layers in the bipolar region;
- forming a first P well at one side of the first isolation layer and a first N well at an opposite side of the first isolation layer;
- forming a deep P well in the bipolar region and a second N well in the deep P well corresponding to one side of the second isolation layer;
- forming a first gate in the first N well and a second gate in the first P well;
- forming a first source/drain by implanting second type impurities into the first N well, and an emitter and a collector by implanting second type impurities into the deep P well and the second N well at both sides of the second isolation layer;
- and then
- forming a second source/drain by implanting the second type impurities into the first P well, and a base by implanting the second type impurities into the second N well at one side of the third isolation layer.
An apparatus comprising:
- a semiconductor substrate including a CMOS region and a bipolar region;
- a first isolation layer formed in the semiconductor substrate;
- a first N well formed in the CMOS region;
- a first P well formed in the CMOS region and separated from the first N well by the first isolation layer;
- a PMOS device formed in the first N well;
- an NMOS device formed in the first P well;
- a deep P well formed in the bipolar region;
- a second N well formed in the deep P well;
- a second isolation layer formed between the deep P well and the second N well to define an emitter region;
- an emitter formed in the deep P well;
- a third isolation layer formed in the second N well defining a base region and a collector region;
- a collector formed in the second N well between the second and third isolation layers;
- and
- a base formed in the second N well at one side of the third isolation layer, the base contacting the emitter.
Dependencies are inferred from the claim text.