Integrated circuitry for semiconductor memory

An integrated circuit comprising:

• a semiconductor die;
• a plurality of functional and operably addressable memory cells arranged on the semiconductor die, each including at least one container-configured capacitor coupling to a word line formed substantially below the at least one container-configured capacitor and each of the plurality of memory cells coupling to a digit line formed substantially above the at least one container-configured capacitor;
• column addressing circuitry formed on the semiconductor die and coupled to the memory cells for addressing columns of the memory cells, and
• sense amplifier circuitry formed on the semiconductor die and coupled to the memory cells for sensing signals from rows of the memory cells;
• wherein the memory cells are formed with a minimum capable photolithographic feature dimension, and a single one of the memory cells consumes an area of no more than eight times the square of the minimum capable photolithographic feature dimension.

An integrated circuit comprising:

• a semiconductor die;
• a plurality of functional and operably addressable memory cells arranged on the semiconductor die, each including at least one container-configured capacitor coupling to a word line formed substantially below the at least one container-configured capacitor and each of the plurality of memory cells coupling to a digit line formed substantially above the at least one container-configured capacitor;
• column addressing circuitry formed on the semiconductor die and coupled to the memory cells for addressing columns of the memory cells, and
• sense amplifier circuitry formed on the semiconductor die and coupled to the memory cells for sensing signals from rows of the memory cells;
• wherein the memory cells are formed with a minimum capable photolithographic feature dimension, and a single one of the memory cells consumes an area of no more than six times the square of the minimum capable photolithographic feature dimension.

A plurality of integrated circuits comprising:

• a processed semiconductor wafer ready for dicing;
• and
• a plurality of die sites on the processed semiconductor wafer;
• wherein a predominant number of the total number of die sites on the processed semiconductor wafer include a plurality of functional and operably addressable memory cells arranged on the semiconductor die, each including at least one container-configured capacitor coupling to a word line formed substantially below the at least one container-configured capacitor and each of the plurality of memory cells coupling to a digit line formed substantially above the at least one container-configured capacitor, and circuitry coupled to the memory cells for permitting data to be written to and read from the memory cells, wherein the memory cells are formed with a minimum capable photolithographic feature dimension, and a single one of the memory cells consumes an area of no more than eight times the square of the minimum capable photolithographic feature dimension.

A plurality of integrated circuits comprising:

• a processed semiconductor wafer ready for dicing;
• and
• a plurality of die sites on the processed semiconductor wafer;
• wherein a predominant number of the total number of die sites on the processed semiconductor wafer include a plurality of functional and operably addressable memory cells arranged on the semiconductor die, each including at least one container-configured capacitor coupling to a word line formed substantially below the at least one container-configured capacitor and each of the plurality of memory cells coupling to a digit line formed substantially above the at least one container-configured capacitor, column addressing circuitry coupled to the memory cells for addressing columns of the memory cells, sense amplifier circuitry coupled to the memory cells for sensing signals from rows of the memory cells, the memory cells are formed with a minimum capable photolithographic feature dimension, and a single one of the memory cells consumes an area of no more than eight times the square of the minimum capable photolithographic feature dimension.