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AssigneeS.O.I.Tec Silicon on Insulator Technologies
InventorsFrédéric Allibert, Sébastien Kerdiles
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The invention specifically relates to methods of fabricating a composite substrate by providing a first insulating layer on a support substrate at a thickness of e1 and providing a second insulating layer on a source substrate at a thickness of e2, with each layer having an exposed face for bonding; providing plasma activation energy in an amount sufficient to activate a portion of the thickness of the face of the first insulating layer emp1 and a portion of the thickness of the face of the second insulating layer emp1; providing a final insulating layer by molecular bonding the activated face of the first insulating layer with the activated face of the second insulating layer; and removing a back portion of the source substrate while retaining an active layer comprising a remaining portion of the source substrate bonded to the support substrate with the final insulating layer interposed therein to form the composite substrate. The thicknesses e1, e2 of the first and second insulating layers are sufficient to provide the final insulating layer with a thickness of 50 nanometers or less, and the plasma activation energy and respective thicknesses e1, e2 of the first and second insulating layers are selected such that only respective thicknesses emp1 and emp2 of the faces of the first insulating layer and the second insulating layer are activated.
A composite substrate comprising at least one final insulating layer interposed between a first interface with a first support substrate of semiconductor material and a second interface between an active layer of semiconductor material, wherein the final insulating layer has a total thickness of no greater than 50 nm, and a density of interface trap (DIT) value of 1011·eV−1·cm−2 or less, at both the first and second interfaces.
A composite substrate comprising at least one final insulating layer interposed between a first interface with a first support substrate of semiconductor material and a second interface between an active layer of semiconductor material selected from the group consisting of silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN) and silicon germanium (SiGe), wherein the final insulating layer is selected from the group consisting of silicon dioxide (SiO2), hafnium dioxide (HfO2), yttrium oxide (Y2O3), strontium and titanium trioxide (SrTiO3), alumina (Al2O3), zirconium dioxide (ZrO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), and their respective nitrides or silicides and has a total thickness of no greater than 50 nm and a density of interface trap (DIT) value of 1011·eV−1·cm−2 or less, at both the first and second interfaces.
Dependencies are inferred from the claim text.