System and method for isolated nmos-based esd clamp cell
AssigneeAnalog Devices, Inc.
InventorsDavid FOLEY, Haiyang ZHU
Life of this patent
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Abstract
The invention is directed to a protection circuit for protecting IC chips against ESD. An ESD protection circuit for an integrated circuit chip may comprise an isolated NMOS transistor, which may comprise an isolation region isolating a backgate from a substrate, and a first and second doped regions and a gate formed on the backgate. The ESD protection circuit may further comprise a first terminal to connect the isolation region to a first electrical node, and a second terminal to connect the second doped region to a second electrical node. The first electrical node may have a higher voltage level than the second electrical node, and the gate and backgate may be coupled to the second terminal.
Claims24
An ESD protection circuit for an integrated circuit chip, comprising:
- an isolated NMOS transistor comprising:
- an isolation region isolating a backgate from a substrate, and
- a first and second doped regions and a gate formed on the backgate;
- a first terminal to connect the isolation region to a first electrical node;
- and
- a second terminal to connect the second doped region to a second electrical node, wherein the first electrical node has a higher voltage level than the second electrical node, and the gate and backgate are coupled to the second terminal.
An ESD protection circuit for an integrated circuit chip, comprising:
- an isolated MOS transistor comprising:
- an isolation region isolating a backgate from a substrate, and
- a first and second doped regions and a gate formed on the backgate;
- a first terminal to connect the isolation region to a first electrical node;
- a second terminal to connect the backgate to a second electrical node;
- and
- a third terminal to connect the first doped region to a third electrical node, wherein the first electrical node has a higher voltage level than the third electrical node and the third electrical node has a higher voltage level than the second electrical node.
An integrated circuit chip, comprising:
- a plastic casing with a plurality of pins;
- an integrated circuit die connected to the pins, the integrated circuit die including an isolated NMOS transistor comprising:
- an isolation region isolating a backgate from a substrate, and
- a first and second doped regions and a gate formed on the backgate;
- a first terminal to connect the isolation region to a first electrical node;
- and
- a second terminal to connect the second doped region to a second electrical node, wherein the first electrical node has a higher voltage level than the second electrical node, and the gate and backgate are coupled to the second terminal via a first resistor and second resistor, the second resistor has an adjustable resistance, the gate is connected to a source of the NMOS transistor.
An integrated circuit chip, comprising:
- a plastic casing with a plurality of pins;
- an integrated circuit die connected to the pins, the integrated circuit die including an isolated NMOS transistor comprising:
- an isolation region isolating a backgate from a substrate, and
- a first and second doped regions and a gate formed on the backgate;
- a first terminal to connect the isolation region to a first electrical node;
- a second terminal to connect the backgate to a second electrical node;
- and
- a third terminal to connect the first doped region to a third electrical node, wherein the first electrical node has a higher voltage level than the third electrical node and the third electrical node has a higher voltage level than the second electrical node, the backgate is to be coupled to the second terminal via a resistor with an adjustable resistance, the gate is connected to a source of the NMOS transistor.
Dependencies are inferred from the claim text.