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US 2010/0140712 A1Published application
Electro Static Discharge Clamping Device
AssigneeInfineon Technologies AG
InventorCornelius Christian Russ
Life of this patent
Estimating the term…
Abstract
Electrostatic discharge clamp devices are described. In one embodiment, the semiconductor device includes a first transistor, the first transistor including a first source/drain and a second source/drain, the first source/drain coupled to a first potential node, the second source/drain coupled to a second potential node. The device further includes a OR logic block, a first input of the OR logic block coupled to the first potential node through a capacitor, the first input of the OR logic block being coupled to the second potential node through a resistor, and a second input of the OR logic block coupled to a substrate pickup node of the first transistor.
Claims41
A semiconductor device comprising:
- a first transistor, the first transistor comprising a first source/drain and a second source/drain, the first source/drain coupled to a first potential node, the second source/drain coupled to a second potential node;
- an OR logic block;
- a first input of the OR logic block coupled to the first potential node through a capacitor, the first input of the OR logic block being coupled to the second potential node through a resistor;
- and
- a second input of the OR logic block coupled to a substrate pickup node of the first transistor.
2 more elements
A semiconductor device comprising:
- a first well region disposed in a substrate, the first well region comprising a first doping type;
- a first source/drain region disposed in the first well region, the first source/drain region being coupled to a first potential node;
- a second source/drain region disposed in the first well region, the first and the second source/drain regions comprising a second doping type, the second doping type being opposite to the first doping type, the second source/drain region being coupled to a second potential node;
- a first gate electrode disposed above the substrate, the first gate electrode disposed between the first and the second source/drain regions, the first gate electrode coupled to an output of a NOR gate through an inverting buffer;
- and
- a pickup region disposed in the first well region, the pickup region comprising the first doping type, the pickup region coupled to an input of the NOR gate.
3 more elements
A semiconductor device comprising:
- a MOS transistor, the MOS transistor comprising a first source/drain and a second source/drain, the first source/drain coupled to a first potential node, the second source/drain coupled to a second potential node;
- an input of a first inverting buffer coupled to a substrate pickup node of the first transistor;
- an input of a second inverting buffer coupled to an output of the first inverting buffer;
- and
- a gate of the MOS transistor coupled to a output of the second inverting buffer.
2 more elements
A semiconductor device comprising:
- a MOS transistor, the MOS transistor comprising a first source/drain and a second source/drain, the first source/drain coupled to a first potential node, the second source/drain coupled to a second potential node;
- a first PMOS transistor, wherein a first source/drain of the first PMOS transistor is coupled to the first potential node;
- a second PMOS transistor, wherein a second source/drain of the first PMOS transistor is coupled to a first source/drain of the second PMOS transistor;
- a first NMOS transistor, wherein a second source/drain of the second PMOS transistor is coupled to a first source/drain of the first NMOS transistor, wherein a second source/drain of the first NMOS transistor is coupled to the second potential node, wherein a gate of the first PMOS transistor and a gate of the first NMOS transistor are coupled to the first potential node through a capacitor;
- a second NMOS transistor, wherein a first source/drain of the second NMOS transistor is coupled to the second source/drain of the PMOS transistor, wherein a second source/drain of the second NMOS transistor is coupled to the second potential node, wherein a gate of the second PMOS transistor and a gate of the second NMOS transistor are coupled to a substrate pickup node of the MOS transistor;
- a third PMOS transistor, wherein a first source/drain of the third PMOS transistor is coupled to the first potential node;
- and
- a third NMOS transistor, wherein a first source/drain of the third NMOS transistor is coupled to a second source/drain of the third PMOS transistor, wherein a second source/drain of the third NMOS transistor is coupled to the second potential node, wherein gates of the third PMOS and NMOS transistors are coupled to the second source/drain of the second PMOS transistor, and wherein the second source/drain of the third PMOS transistor is coupled to the gate of the MOS transistor.
5 more elements
A semiconductor device comprising:
- a MOS transistor, the MOS transistor comprising a first source/drain and a second source/drain, the first source/drain coupled to a first potential node, the second source/drain coupled to a second potential node;
- a AND logic block;
- a first input of the AND logic block coupled to the first potential node through a resistor, the first input of the AND logic block being coupled to the second potential node through a capacitor;
- and
- a second input of the AND logic block coupled to a substrate pickup node of the MOS transistor.
2 more elements
Dependencies are inferred from the claim text.