Simultaneous via and trench patterning using different etch rates

A method for forming a metal level and a via level within a single inter-level dielectric layer, comprising:

• providing a semiconductor substrate comprising a conductive layer positioned on the substrate;
• forming an inter-level dielectric layer of a dual damascene structure on the semiconductor substrate;
• performing a lithography process that forms a photoresist layer above the inter-level dielectric to define a pattern of a via hole having a first critical dimension and one or more metal line trenches having a second critical dimension, wherein the first critical dimension is larger than the second critical dimension;
• and
• performing a first etching process according to the pattern of the photoresist layer to remove the inter-level dielectric layer not covered by the pattern of the photoresist layer, the removal proceeding at different etch rates for the via hole and the one or more metal wires determined by differences in the first and second critical dimensions, so as to simultaneously form the via hole extending through the inter-level dielectric layer and the one or more metal line trenches extending only within an upper part of the inter-level dielectric layer.

A method for fabricating an integrated circuit including metal and via levels formed within a layer of inter-level dielectric material, the method comprising:

• forming an inter-level dielectric layer over a substrate;
• forming a mask over the inter-level dielectric layer;
• patterning the mask to provide a mask via region defining a via opening having a first critical dimension and a mask wire region defining one or more trench openings having a second critical dimension, the second critical dimension being less than the first critical dimension;
• simultaneously etching the inter-level dielectric layer at a first vertical etch rate through the mask via region and at a second vertical etch rate through the mask wire region, the first and second vertical etch rates being determined by the respective sizes of the first and second critical dimensions, so that the via opening is formed through the inter-level dielectric layer by etching at the first vertical etch rate at the same time as the one or more trench openings are formed only partway into the inter-level dielectric layer by etching at the second vertical etch rate;
• and
• filling the via opening and the one or more trench openings with conductive material.