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US 2010/0072569 A1Published application
Method of forming an isolation layer, method of manufacturing a semiconductor device using the same, and semiconductor device having an isolation layer
AssigneeSamsung Electronics Co., Ltd.
InventorsTae-Jong Han, Mun-Jun Kim, Deok-Young Jung, Eun-Kyung Baek, Ju-Seon Goo
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Abstract
In a method of forming an isolation layer, a plurality of trenches is formed on a substrate. A liner is formed on inner walls of the trenches. The liner is thermally oxidized to fill up some of the trenches. The other trenches are filled up with an insulation material. As a result, the isolation layer is free of voids.
Claims20
A method of forming an isolation layer, comprising:
- forming a plurality of trenches on a substrate, the trenches having aspect ratios different from each other;
- forming a liner on inner walls of the trenches;
- thermally oxidizing the liner to fill up some of the trenches having relatively high aspect ratios;
- and
- filling up the other trenches having relatively low aspect ratios with an insulation material.
2 more elements
A method of manufacturing a semiconductor device, comprising:
- forming a plurality of trenches on a substrate including a cell region and a peripheral region, the trenches having aspect ratios different from each other;
- forming a liner on inner walls of the trenches;
- thermally oxidizing the liner to fill up some of the trenches having relatively high aspect ratios to form a first isolation layer;
- filling up the other trenches having relatively low aspect ratios with an insulation material to form a second isolation layer;
- forming a gate structure on the substrate having the first and second isolation layers thereon;
- forming an impurity region at an upper portion of the substrate;
- and
- forming a capacitor to be electrically connected to the impurity region.
5 more elements
A semiconductor device comprising:
- a first isolation layer including a nitride liner and an oxynitride layer sequentially stacked on a substrate, the substrate including a cell region and a peripheral region;
- a second isolation layer including the nitride liner, the oxynitride layer and an SOG layer sequentially stacked on the substrate;
- a gate structure on the substrate having the first and second isolation layers thereon;
- an impurity region at an upper portion of the substrate;
- and
- a capacitor electrically connected to the impurity region.
3 more elements
Dependencies are inferred from the claim text.