A method for forming a multi-layer shallow trench isolation structure in a semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShu-Tine Yang, Chen-Hua Yu, Chu-Yun Fu
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShu-Tine Yang, Chen-Hua Yu, Chu-Yun Fu
Estimating the term…
The disclosure describes a multi-layer shallow trench isolation structure in a semiconductor device. The shallow trench isolation structure may include a first void-free, doped oxide layer in the shallow trench, and a second void-free layer above the first doped oxide layer. The first layer may be formed by vapor deposition of precursors of a source of silicon, a source of oxygen and sources of doping materials and making the layer void-free by reflowing the initial layer by an annealing process. The second layer may be formed by vapor deposition of precursors of silicon and doping materials and making the layer void-free by reflowing the initial layer by an annealing process. Alternatively, the second layer may be a silicon oxide layer that may be formed by an atomic layer deposition method. The processing conditions for forming the two layers are different.
A multi-layer shallow trench isolation structure in a semiconductor device, the structure comprising:
(canceled)
The method of claim 12, wherein:
A method for forming a multi-layer shallow trench isolation structure in a semiconductor device, the method comprising the steps of:
(canceled)
The method of claim 18, wherein:
A method for forming a multi-layer shallow trench isolation structure in a semiconductor device, the method comprising the steps of:
(canceled)
Dependencies are inferred from the claim text.