Capacitor Pairs with Improved Mismatch Performance

An integrated circuit device comprising:

• a capacitor array comprising a first plurality of unit capacitors and a second plurality of unit capacitors, wherein a total number of unit capacitances in the capacitor array is no less than six, and wherein the first and the second pluralities of unit capacitors are placed in an alternating pattern in each row and each column of the capacitor array;
• wherein each unit capacitor in the first plurality of unit capacitors comprises:
• a first common node comprising a first conductive bus and a plurality of first fingers connected to the first conductive bus;
• a plurality of second fingers, each being between and electrically insulated from two of the plurality of first fingers;
• and
• a second conductive bus interconnecting the plurality of second fingers;
• wherein each unit capacitor in the second plurality of unit capacitors comprises:
• a second common node comprising a third conductive bus and a plurality of third fingers connected to the third conductive bus;
• a plurality of fourth fingers, each being between and electrically insulated from two of the plurality of third fingers;
• and
• a fourth conductive bus interconnecting the plurality of fourth fingers;
• and
• wherein the first common nodes of the unit capacitors in the first plurality of unit capacitors are interconnected, the second common nodes of the unit capacitors in the second plurality of unit capacitors are interconnected, the second conductive buses of the unit capacitors in the first plurality of unit capacitors are interconnected, and the fourth conductive buses of the unit capacitors in the second plurality of unit capacitors are interconnected.

A semiconductor device comprising:

• a first capacitor comprising a first plurality of unit capacitors interconnected to each other, each having a first unit capacitance of less than about 200fF or a first unit area of less than about 200 um2;
• a second capacitor comprising a second plurality of unit capacitors interconnected to each other, each having a second unit capacitance of less than about 200fF or a second unit area of less than about 200 um2, wherein the first and the second pluralities of unit capacitors have a same number of unit capacitors, and wherein the first and the second pluralities of unit capacitors are arranged as an array and are placed in an alternating pattern in each row and each column of the array;
• and
• a common node interconnecting the first plurality of unit capacitors to the second plurality of unit capacitors.