Semiconductor design apparatus, semiconductor circuit and semiconductor design method
AssigneeKabushiki Kaisha Toshiba
InventorsHiroshige Orita, Kazunari Kimura, Toshiaki Mori
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Abstract
According to an aspect of the present invention, there is provided a semiconductor design apparatus including: a determination section that determines a connection position of a capacitor to suppress a noise on a layout data in which a layout of circuit cells are completed; a calculation section that calculates a capacitance value required to suppress the noise; a generation section that generates the capacitor satisfying the capacitance value; and a wiring section that wires the capacitor to a power wiring and a ground wiring at the connection position.
Claims13
A semiconductor design apparatus comprising:
- a determination section that determines a connection position of a capacitor to suppress a noise on a layout data in which a layout of circuit cells are completed;
- a calculation section that calculates a capacitance value required to suppress the noise;
- a generation section that generates the capacitor satisfying the capacitance value;
- and
- a wiring section that wires the capacitor to a power wiring and a ground wiring at the connection position.
A semiconductor circuit comprising:
- a capacitor cell including:
- a capacitor element that has a capacitance to suppress a noise;
- and
- capacitor terminals that are connected to the capacitor element and that are disconnected from a power wiring and a ground wiring at a position where the capacitor element is placed.
A method for designing semiconductor, comprising:
- inputting a layout data in which a layout of circuit cells are completed;
- determining a connection position of a capacitor to suppress a noise on the layout data;
- calculating a capacitance value required to suppress the noise;
- generating a capacitor satisfying the calculated capacitance value on a periphery area of the connection position;
- and
- wiring the capacitor to a power wiring and a ground wiring at the determined connection position.
Dependencies are inferred from the claim text.