Dual trench isolation for cmos with hybrid orientations

A method of fabricating a semiconductor structure comprising:

• providing a hybrid substrate comprising a first lower semiconductor layer of a first crystallographic orientation and a second upper semiconductor layer of a second crystallographic orientation which differs from the first crystallographic orientation, wherein a conductive bonding interface separates said semiconductor layers from each other;
• providing at least one opening of a first depth in said hybrid substrate which exposes said first lower semiconductor layer;
• forming a spacer within said at least one opening having said first depth;
• regrowing a semiconductor material on said exposed first lower semiconductor layer, said semiconductor material having said first crystallographic orientation;
• planarizing said semiconductor material to an upper surface of said second upper semiconductor layer to provide a structure having at least two coplanar surfaces of different crystallographic orientation;
• and
• forming trench isolation regions having a second depth which is shallower than the first depth of said opening in said at least two coplanar surfaces, wherein said spacer provides isolates between the coplanar surfaces of different crystallographic orientations.