Nitride-encapsulated fet (nncfet)
AssigneeInternational Business Machines Corporation
InventorsKevin K. Chan, Hussein I. Hanafi, Paul M. Solomon
Life of this patent
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Abstract
A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.
Claims11
A method of fabricating a double-gate field effect transistor comprising the steps of:
- providing a structure which includes at least a doped back-plane region, a back-gate dielectric stack including at least a bottom back-gate nitride formed atop said doped back-plane region, a Si-containing layer having edges formed atop said back-gate dielectric stack, a front gate dielectric formed atop said Si-containing layer, and a front gate formed atop said front gate dielectric, said structure having isolation trench regions adjacent to at least said doped back-plane region;
- forming insulating spacers on exposed vertical sidewalls of said front gate;
- forming protective spacers on said structure about said insulating spacers and coveting said edges of said Si-containing layer;
- forming isolation regions in regions of said structure which are adjacent to, and overlaying a portion of said doped back-plane region, whereby said protective spacers and said bottom back-gate nitride protect said Si-containing layer from oxidizing;
- removing said protective spacers exposing said edges of said Si-containing layer;
- and
- selectively growing Si-containing regions above and in contact with said edges.
Dependencies are inferred from the claim text.