Semiconductor device and memory and method of operating thereof
AssigneeMacronix International Co., Ltd.
InventorChao-I Wu
Life of this patent
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Abstract
A memory applicable to an embedded memory is provided. The memory includes a substrate, a gate, a charge-trapping gate dielectric layer, a source, and a drain. The gate is disposed above the substrate. The charge-trapping gate dielectric layer is disposed between the gate and the substrate. The source and the drain are disposed in the substrate beside the gate respectively.
Claims28
A semiconductor device, comprising:
- a substrate has a logic circuit region and a memory region;
- a metal oxide semiconductor transistor, disposed in the logic circuit region, and the metal oxide semiconductor transistor comprising a substrate, a drain and a source disposed in the substrate, a gate disposed between the drain and the source and above the substrate, and a gate dielectric layer disposed between the gate and the substrate;
- and
- a memory, disposed in the memory region, the memory and the metal oxide semiconductor transistor are the same stacked structure having the same material, and the memory comprising a substrate, a drain and a source disposed in the substrate, a gate disposed between the drain and the source and above the substrate, and a charge-trapping gate dielectric layer disposed between the gate and the substrate.
A memory, applicable to an embedded memory, the memory comprising:
- a substrate;
- a gate, disposed above the substrate;
- a charge trapping gate dielectric layer, disposed between the gate and the substrate;
- and
- a source and a drain, disposed in the substrate beside the gate respectively.
A method of operating a memory, the memory comprising a substrate, a drain and a source disposed in the substrate, a gate disposed between the drain and the source and above the substrate, and a charge-trapping gate dielectric layer disposed between the gate and the substrate, the operating method comprising:
- performing an erasing operation, wherein a first gate voltage is applied on the gate, a first drain voltage is applied on the drain, a first source voltage is applied on the source, and a first substrate voltage is applied on the substrate, so as to inject holes into the charge-trapping gate dielectric layer to erase the memory;
- and
- performing a programming operation, wherein a second gate voltage is applied on the gate, a second drain voltage is applied on the drain, a second source voltage is applied on the source, and a second substrate voltage is applied on the substrate, so as to pull the holes from the charge-trapping gate dielectric layer to the substrate to program the memory.
Dependencies are inferred from the claim text.