Memory cell with independent-gate controlled access devices and memory using the cell

A memory circuit comprising:

• a plurality of bit line structures, said bit line structures in turn comprising true and complementary bit lines;
• a plurality of word lines structures, said word line structures in turn comprising READ and WRITE word lines, said word line structures intersecting said plurality of bit line structures to form a plurality of cell locations;
• a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding one of said bit line structures under control of a corresponding one of said word line structures, each of said cells in turn comprising:
• a first inverter having a first inverter double-gate pull-down device;
• a second inverter having a second inverter double-gate pull-down device, said second inverter being cross-coupled to said first inverter to form a storage flip-flop;
• and
• first and second access devices configured to selectively interconnect said cross-coupled inverters with said true and complementary bit lines of a corresponding one of said word line structures, said first and second access devices being double-gate devices, each having a first gate connected to said READ word line and a second gate connected to said WRITE word line;
• and
• control circuitry connected to said bit line structures and said word line structures and configured to:
• activate said READ word line but not said WRITE word line during a READ operation, so that said first and second access devices operate in a single-gate mode while said double-gate pull-down devices operate in a double gate mode;
• and
• activate both said READ word line and said WRITE word line during a WRITE operation, so that said first and second access devices operate in a double-gate mode.