Dual stress liner

Abstract

A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second source region, a second drain region and a second gate conductor overlying the second channel region. The first and second gate conductors can be portions of a single elongated conductive member extending over both the first and second channel regions. A first stressed film may overlie the first FET and the first stressed film may apply a stress having a first value to the first channel region. A second stressed film may overlie the second FET and the second stressed film may apply a stress having a second value to the second channel region. The second value is substantially different from the first value. The first and second stressed films can abut each other at a common boundary and present a substantially co-planar major surface at the common boundary.

Dependencies are inferred from the claim text.