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AssigneeInternational Business Machines Corporation
InventorsToshijaru Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, Chung H. Lam, Gerhard I. Meijer
Estimating the term…
Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.
A semiconductor structure that allows for simultaneous conditioning of multiple parallel memory elements in devices with multiple memory cells, said semiconductor structure comprising:
A semiconductor structure that allows for simultaneous conditioning of multiple parallel memory elements in devices with multiple memory cells, said semiconductor structure comprising:
A method of simultaneously conditioning multiple memory elements in devices with multiple memory cells, wherein said memory elements comprise a transition metal oxide layered between first electrodes and second electrodes, said method comprising:
A method of simultaneously conditioning multiple memory elements in devices with multiple memory cells, wherein said memory elements comprise a transition metal oxide layered between first electrodes and second electrodes, said method comprising:
Dependencies are inferred from the claim text.