Stacked gate nonvolatile semiconductor memory and method for manufacturing the same

A stacked gate nonvolatile semiconductor memory comprising at least a memory cell transistor and a selective gate transistor which are formed on a semiconductor substrate;

• wherein said memory cell transistor includes a floating gate made of a semiconductor material below an interlayer insulating layer and a control gate made of a silicide above said interlayer insulating layer;
• wherein said selective gate transistor includes a semiconductor layer made of said semiconductor material, a silicide layer made of said silicide and a silicide conductive layer made of an additional silicide material which is formed through said interlayer insulating film so as to electrically connect said semiconductor layer and said silicide layer.

A stacked gate nonvolatile semiconductor memory comprising at least a memory cell transistor and a selective gate transistor which are formed on a semiconductor substrate;

• wherein said memory cell transistor includes a floating gate made of a semiconductor material below an interlayer insulating layer and a control gate made of a silicide above said interlayer insulating layer;
• wherein said selective gate transistor includes a semiconductor layer made of said semiconductor material and a conductive layer made of a conductive material not subject to silicide process which is formed on said semiconductor layer.

A stacked gate nonvolatile semiconductor memory comprising at least a memory cell transistor and a selective gate transistor which are formed on a semiconductor substrate;

• wherein said memory cell transistor includes a floating gate made of a semiconductor material below an interlayer insulating layer and a control gate made of a silicide above said interlayer insulating layer;
• wherein said selective gate transistor includes a semiconductor layer made of said semiconductor material and a silicide conductive layer made of an additional silicide material.

A method for manufacturing a stacked gate nonvolatile semiconductor memory, comprising:

• forming, on a semiconductor substrate, a memory cell transistor including a floating gate made of a semiconductor material located below an interlayer insulating film and a control gate made of a silicide located above said interlayer insulating film;
• subsequently forming a semiconductor layer of said semiconductor material and a silicide layer of said silicide via said interlayer insulating film, and partially removing at least said semiconductor layer and said interlayer insulating film to form an opening, and forming a conductive layer made of a conductive material not subject to silicide process in said opening to form a selective gate transistor.

A method for manufacturing a stacked gate nonvolatile semiconductor memory, comprising:

• forming, on a semiconductor substrate, a memory cell transistor including a floating gate made of a semiconductor material located below an interlayer insulating film and a control gate made of a silicide located above said interlayer insulating film;
• and
• subsequently forming a semiconductor layer of said semiconductor material and a silicide layer of said silicide via said interlayer insulating film, and partially removing at least said semiconductor layer and said interlayer insulating film to form an opening, and forming a silicide conductive layer made of an additional silicide in said opening to form a selective gate transistor.

A method for manufacturing a stacked gate nonvolatile semiconductor memory, comprising:

• forming, on a semiconductor substrate, a memory cell transistor including a floating gate made of a semiconductor material located below an interlayer insulating film and a control gate made of a silicide located above said interlayer insulating film;
• and
• subsequently forming a semiconductor layer of said semiconductor material and a pre-semiconductor layer via interlayer insulating film, and removing said pre-semiconductor layer, said interlayer insulating film and a portion of said semiconductor layer in the stacking direction thereof, and forming, on the remaining semiconductor layer, a conductive layer made of a conductive material not subject to silicide process to form a selective gate transistor.

A method for manufacturing a stacked gate nonvolatile semiconductor memory, comprising:

• forming, on a semiconductor substrate, a memory cell transistor including a floating gate made of a semiconductor material located below an interlayer insulating film and a control gate made of a silicide located above said interlayer insulating film;
• and
• subsequently forming a semiconductor layer of said semiconductor material and a pre-semiconductor layer via interlayer insulating film, and removing said pre-semiconductor layer, said interlayer insulating film and a portion of said semiconductor layer in the stacking direction thereof, and forming, on the remaining semiconductor layer, a silicide conductive layer made of an additional silicide to form a selective gate transistor.