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US 2008/0166839 A1Published application
Sub-lithographics opening for back contact or back gate
AssigneeTexas Instruments Incorporated
InventorTheodore W. Houston
Life of this patent
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Abstract
A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in the trench to decrease its width to sublithographic dimension. Conducting material is deposited in the trench, which serves as a low-resistance contact to the back side of the device. In another embodiment, the trench-fill material is separated from the device by an insulating layer, and serves as a back gate structure.
Claims9
1-21. (canceled)
A fabrication method, comprising the steps of:
- providing a semiconductor material with an insulating layer thereon;
- etching a trench in said insulating layer;
- forming sidewalls in said trench;
- forming a conducting material in said trench;
- wherein said semiconductor material has a transistor formed therein;
- and
- wherein said conducting material is aligned with the channel of said transistor.
4 more elements
A fabrication method, comprising the steps of:
- providing a substrate with an insulating layer thereon;
- forming a trench in said insulating layer;
- forming sidewalls in said trench;
- filling said trench with a conducting material;
- forming a transistor over said trench.
2 more elements
Dependencies are inferred from the claim text.