Method for forming metal interconnection of semiconductor device
AssigneeDongbu HiTek Co., Ltd.
InventorJi Ho Hong
Life of this patent
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Abstract
Disclosed is a method for forming a metal interconnection in a semiconductor device. In a damascene process, a capping barrier metal layer is formed generally only on a lower metal interconnection in order to prevent the diffusion of atoms from the lower metal interconnection into an upper dielectric layer. The capping barrier metal layer prevents the increase of an effective dielectric constant of a lower inter-metal dielectric layer that surrounds the lower metal interconnection, and may reduce the resistance of the metal interconnection, thereby improving the reliability, speed and/or other characteristics of the semiconductor device.
Claims18
A method for forming an interconnection in a semiconductor device, the method comprising the steps of:
- (a) forming a first barrier layer on an inner wall of a first via hole in a first dielectric layer on a semiconductor substrate, and forming a first metal interconnection on the first barrier layer;
- (b) stacking an insulating layer on the semiconductor substrate;
- (c) forming a first trench in the insulating layer;
- (d) forming a second barrier layer on an inner wall of the first trench and a second metal interconnection on the second barrier layer;
- (e) forming a lower capping barrier metal layer on the second metal interconnection;
- (f) forming a second dielectric layer;
- (g) forming a second via hole and a second trench in the second dielectric layer;
- (h) forming a third barrier layer on inner walls of the second via hole and the second trench, and forming an upper metal interconnection on the third barrier;
- and
- (i) forming an upper capping barrier metal layer on the trench of the second dielectric layer.
A method for forming a metal interconnection in a semiconductor device, the method comprising the steps of:
- (a) forming a via hole in an insulating layer on a semiconductor substrate;
- (b) forming a trench on the via hole;
- (c) stacking a barrier metal layer;
- (d) stacking a metal interconnection;
- (e) polishing the barrier metal layer and the metal interconnection until the insulating layer is exposed;
- and
- (f) forming a capping barrier metal layer on the metal interconnection.
A semiconductor device comprising:
- (a) a semiconductor substrate having an isolation layer, a high-density junction area, a gate insulating layer and a gate electrode;
- (b) a first insulating layer on the semiconductor substrate;
- (c) a first via hole in the first insulating layer, the via hole having a first barrier layer on an inner wall of the via hole and a first metal interconnection on the first barrier layer;
- (d) a first trench on the via hole, the first trench having a second barrier layer on an inner wall of the first trench and a second metal interconnection on the second barrier layer;
- (e) a lower capping barrier metal layer covering the second metal interconnection in the trench;
- (f) a second insulating layer on the first insulating layer;
- (g) a second via hole and a second trench in the second insulating layer;
- (h) a third barrier layer on inner walls of the second via hole and the second trench;
- (i) an upper metal interconnection on the third barrier layer;
- and
- (j) an upper capping barrier metal layer formed the upper metal interconnection.
Dependencies are inferred from the claim text.