Memory cell arrangements and methods of manufacturing memory cell arrangements

A method of manufacturing a memory cell arrangement, the method comprising:

• forming a first memory cell string comprising a plurality of serially source-to-drain-coupled transistors, at least some of the transistors being memory cells;
• forming a second memory cell string comprising a plurality of serially source-to-drain-coupled transistors, at least some of the transistors being memory cells;
• forming dielectric material between and above the plurality of transistors of the first memory cell string and the plurality of transistors of the second memory cell string;
• forming a source/drain line groove in the dielectric material, the source/drain line groove extending from a source/drain region of one transistor of the plurality of transistors of the first memory cell string to a source/drain region of one transistor of the plurality of transistors of the second memory cell string;
• at least partially filling electrically conductive filling material into the source/drain line groove coupled to the source/drain region of the transistor of the plurality of transistors of the first memory cell string and to the source/drain region of the transistor of the plurality of transistors of the second memory cell string;
• removing the electrically conductive filling material in a region between the transistor of the plurality of transistors of the first memory cell string and the source/drain region of the transistor of the plurality of transistors of the second memory cell string;
• and
• at least partially filling dielectric filling material into the source/drain line groove in those regions in which the electrically conductive filling material has been removed.