Integrated lithography and etch for dual damascene structures
AssigneeInternational Business Machines Corporation
InventorsShom Ponoth, William America, Timothy Brunner, Ronald DellaGuardia, Kaushal Patel
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Abstract
A method and structure for an integrated via and line lithography followed by integrated via and line etch. A two-layered, negative resist based lithography is used to generate a dual damascene structure in the photoresist which is subsequently transferred into the underlying ILD using an lithography with an integrated RIE. A method is also provided to correct any misalignment between the via and trench during photolithography steps which would reduce the size of the via opening and impact the via resistance.
Claims21
A method of dual damascene patterning through the use of a two-layered negative resist comprising the steps of:
- providing a semiconductor substrate having an interlayer dielectric layer deposited thereon;
- forming a first negative resist layer on said interlayer dielectric layer;
- hole patterning said first negative resist layer by exposing and developing said first negative resist layer using a via level level mask;
- forming a second negative resist layer on said first negative resist layer;
- and
- line patterning said second negative resist layer by exposing and developing said second negative resist layer using a line level mask, thereby forming a via and line structure in the undeveloped resist.
A method of dual damascene patterning through the use of a two-layered negative resist comprising the steps of:
- providing a semiconductor substrate having an interlayer dielectric layer deposited thereon;
- forming a first negative resist layer on said interlayer dielectric layer;
- exposing said first negative resist layer using a via level level mask;
- forming a second negative resist layer on said first negative resist layer;
- and
- hole and line patterning said first and second negative resist layers by exposing and developing said first and second negative resist layers using a line level mask, thereby forming a via and line structure in the undeveloped resist.
A method of dual damascene patterning through the use of a two-layered negative resist and integrated RIE process comprising the steps of:
- providing a semiconductor substrate having a cap layer thereon and an interlayer dielectric layer deposited on said cap layer;
- providing an etch stop layer on said interlayer dielectric layer and an organic layer on said etch stop layer;
- providing a hardmask layer on said organic layer;
- forming a first negative resist layer on said hardmask layer;
- hole patterning said first negative resist layer by exposing and developing said first negative resist layer using a via level level mask;
- forming a second negative resist layer on said first negative resist layer;
- and
- line patterning said second negative resist layer by exposing and developing said second negative resist layer using a line level mask, thereby forming a via and line structure in the undeveloped resist;
- and
- performing an oxide RIE to remove portions of said hardmask layer and transfer said via pattern into the surface of said organic layer.
A dual damascene structure comprising:
- a semiconductor substrate having an interlayer dielectric layer deposited thereon;
- a first negative resist layer on said interlayer dielectric layer, said first negative resist layer having developed first negative resist features therein;
- a second negative resist layer on said first negative resist layer, said second negative resist layer having developed second negative resist features therein;
- and
- said second developed negative resist features having an area greater than or equal to the area of said first developed negative resist features.
Dependencies are inferred from the claim text.