Single stress liner for migration stability and speed
OwnerJoseph Chan, Robert Wonginventors
Life of this patent
Estimating the term…
Abstract
A single stress liner is applied over different type semiconductor devices. The single stress liner avoids the problems of a dual/hybrid stress liner scheme by eliminating the meeting area. The single stress liner may be tensile or compressive. In one embodiment, the semiconductor device includes a static random access memory (SRAM) cell having numerous NFETs and PFETs. In this case, a compressive liner is placed over the SRAM cell, which is normally not ideal for the NFETs therein, but is desirable for the SRAM cell because continued miniaturization of the SRAMs typically requires slowing of the NFETs for the SRAM to maintain stabile. Where SRAM cells require increased speed, a single tensile stress liner can be implemented.
Claims16
A static random access memory (SRAM) cell comprising:
- a plurality of n-type field effect transistors (NFETs);
- a plurality of p-type field effect transistors (PFETs);
- and
- a single stress liner applied over the plurality of NFETs and the plurality of PFETs.
A method of stabilizing a static random access memory (SRAM) cell including a plurality of n-type field effect transistors (NFETs) and a plurality of p-type FETs (PFETs), the method comprising the steps of:
- providing the SRAM cell;
- and
- forming a single compressive stress liner over the plurality of NFETs and the plurality of PFETs.
A method of increasing speed of a static random access memory (SRAM) cell including a plurality of n-type field effect transistors (NFETs) and a plurality of p-type FETs (PFETs), the method comprising the steps of:
- providing the SRAM cell;
- and
- forming a single tensile stress liner over the plurality of NFETs and the plurality of PFETs.
A semiconductor device comprising:
- a plurality of n-type field effect transistors (NFETs);
- a plurality of p-type field effect transistors (PFETs);
- and
- a single stress liner applied over the plurality of NFETs and the plurality of PFETs.
Dependencies are inferred from the claim text.