Sealed nitride layer for integrated circuits
AssigneeIntersil Americas Inc.
InventorJames Beasom
Life of this patent
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Abstract
The present invention relates to an integrated circuit. The integrated circuit includes a substrate, at least one device region formed in the substrate, a patterned layer of oxide, a first and second layer of nitride and at least one metal contact region. The patterned layer of oxide is formed over a surface of the substrate, wherein the patterned layer provides at least one opening to the surface of the substrate adjacent the at least one device region. The first layer of nitride is formed over the patterned oxide layer. The second nitride layer is formed along sidewalls to the at least one opening. The patterned oxide layer is sealed with the first and second nitride layers. The at least one metal contact region is formed in the at least one opening.
Claims17
An integrated circuit comprising:
- a substrate;
- a plurality semiconductor devices formed in the substrate, some of the semiconductor devices having device regions formed adjacent a surface of the substrate;
- a layer of oxide overlaying the surface of the substrate;
- a first layer of nitride overlaying the layer of oxide, the first layer of nitride and the layer of oxide having a plurality of contact openings extending to select device regions in the substrate;
- and
- portions of a second layer of nitride overlaying sidewalls of each contact opening, wherein the portions of the second layer of nitride overlaying the oxide layer in the sidewalls are thinner than the first layer of nitride overlaying the rest of the layer of oxide.
An integrated circuit comprising:
- a substrate;
- at least one device region formed in the substrate;
- a patterned layer of oxide formed over a surface of the substrate, wherein the patterned layer provides at least one opening to the surface of the substrate adjacent the at least one device region;
- a first layer of nitride formed over the patterned oxide layer;
- a second nitride layer formed along sidewalls to the at least one opening, the patterned oxide layer being sealed with the first and second nitride layers;
- and
- at least one metal contact region formed in the at least one opening, wherein the metal contact region is separated from the patterned layer of oxide by the first and second nitride layers.
An integrated circuit having a NPN transistor, the integrated circuit comprising:
- a substrate having a surface;
- a base formed in the substrate adjacent the surface of the substrate;
- an emitter formed in the base region adjacent the surface of the substrate;
- a collector contact formed in the substrate adjacent the surface of the substrate;
- an oxide layer overlaying the surface of the substrate, the oxide layer being patterned to have a first opening to the base, a second opening to the emitter and third opening to the collector contact;
- a first layer of nitride overlaying the oxide layer;
- and
- a second layer of nitride overlaying sidewalls to the first, second and third openings, wherein the first and second layers of nitride seal the oxide layer.
Dependencies are inferred from the claim text.