US 2006/0186487 A1 · PMOS transistor with increased effective channel length in the peripheral region and method of manufacturing the same

Abstract

In manufacturing a PMOS transistor, a semiconductor substrate having an active region and a field region is formed with a hard mask layer, which covers a center portion of the active region on the substrate in a lengthwise direction of a channel. The hard mask layer exposes the center portion of the active region in a widthwise direction of the channel and covers both edges of the substrate and the field region adjacent to the both edges. The substrate is etched to a predetermined depth using the hard mask layer as an etching barrier. The hard mask layer is then removed. A gate covering the center portion of the active region is formed on the lengthwise direction of the channel. Source and drain regions are formed at both edges of the gate.

Claims15

Dependent claims

A PMOS transistor having a semiconductor substrate having an active region and an field region surrounding the active region, the PMOS transistor comprising:

a channel area running across the active region from a first field area formed on at least a predetermined portion of the field region to a second field area formed on at least another predetermined portion of the field region,
wherein the first and second field areas are formed such that a predetermined depth exists between the surface of the first and second field areas and the rest of the active and field regions of the semiconductor substrate, and
wherein the first field area extends into the active region by a first width, and wherein the second field area extends into the active region by a second width wherein the first and second widths are same or different from each other,
a gate formed on the channel area of the semiconductor substrate.

1 more element

A method of manufacturing a PMOS transistor, comprising the steps of:

providing a semiconductor substrate having an active region and a field region having a first field area and a second field area,
wherein a channel area is formed by the first field area, the second field area, and the predetermined portion of the active region between the first and second field areas, and
wherein each of the first and second field areas is capable of being formed to cover a portion of the active region extending from the respective first or second field area;
forming an isolation layer in the field region of the semiconductor substrate;
forming a hard mask layer on each of the first and second field areas;
etching the semiconductor substrate to a predetermined depth by using the hard mask layer as an etching barrier, wherein the predetermined depth exists between the surface of the first and second field areas and the rest of the active and field regions of the semiconductor substrate;
removing the hard mask layer;
forming a gate on the channel area;
and
forming source and drain regions at both edges of the gate on a surface of the semiconductor substrate.

7 more elements

Dependencies are inferred from the claim text.

PMOS transistor with increased effective channel length in the peripheral region and method of manufacturing the same

Life of this patent

PMOS transistor with increased effective channel length in the peripheral region and method of manufacturing the same

Life of this patent

Abstract

Claims15