Method of forming DRAM device having capacitor and DRAM device so formed

A method of forming a capacitor comprising:

• forming at least one interlayer dielectric layer on a semiconductor substrate;
• sequentially etching the at least one interlayer dielectric layer and a portion of the semiconductor substrate to form a storage node hole;
• conformally forming a lower electrode layer in the storage node hole and on the interlayer dielectric layer;
• performing a planarization process to remove a portion of the lower electrode layer that lies on the interlayer dielectric layer and to form a lower electrode in the storage node;
• sequentially forming a dielectric layer and an upper electrode layer on the lower electrode;
• and
• sequentially patterning the upper electrode layer and dielectric layer.

A DRAM device comprising:

• a first well having a first depth in a semiconductor substrate;
• a second well having a second depth shallower than the first depth in the first well;
• a device isolation layer in the semiconductor substrate to define an active region;
• a gate pattern formed on the semiconductor substrate;
• a first impurity implantation region being formed in the active region at both sides of the gate pattern and having a third depth shallower than the second depth;
• at least one interlayer dielectric layer covering the gate pattern and the semiconductor substrate;
• a cup-shaped lower electrode formed through the at least one interlayer dielectric layer and through a portion of the semiconductor substrate, the cup-shaped electrode located at one side of the gate pattern, wherein an upper surface of the lower electrode has the same height as that of the interlayer dielectric layer;
• a dielectric layer coating an inner sidewall and a bottom of the lower electrode, and a portion of the interlayer dielectric layer around a top of the lower electrode;
• and
• an upper electrode on the dielectric layer.

A method of forming a DRAM device comprising:

• forming a first well having a first depth in a semiconductor substrate;
• forming a second well having a second depth shallower than the first depth in the semiconductor substrate;
• forming a device isolation layer in the semiconductor substrate to define an active region;
• forming a gate pattern on the semiconductor substrate;
• forming a first impurity implantation region having a third depth shallower than the second depth in the active region at both sides of the gate pattern;
• forming at least one interlayer dielectric layer on the semiconductor substrate;
• sequentially patterning the at least one interlayer dielectric layer at one side of the gate pattern and a portion of the semiconductor substrate to form a storage node hole;
• conformally forming a lower electrode layer in the storage node hole and on the interlayer dielectric layer;
• performing a planarization process to remove a portion of the lower electrode layer that lies on the interlayer dielectric layer and to form a lower electrode in the storage node hole;
• sequentially forming a dielectric layer and an upper electrode layer on the lower electrode;
• and
• sequentially patterning the upper electrode layer and the dielectric layer.