Semiconductor storage device
AssigneeRenesas Technology Corp.
InventorsHidenori Sato, Hiroyasu Nousou, Yoshitaka Fujiishi, Hiroaki Sekikawa
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AssigneeRenesas Technology Corp.
InventorsHidenori Sato, Hiroyasu Nousou, Yoshitaka Fujiishi, Hiroaki Sekikawa
Estimating the term…
A semiconductor storage device is provided, which inhibits shorts between cells to improve operational reliability and contributes to high-speed operation. An active region (7) where DRAM cells are formed is defined by an isolation trench (40) formed in a silicon substrate (1). The isolation trench (40) has an isolation insulating film (4) formed therein. Each DRAM cell includes a MOS transistor having a gate electrode (12) with sidewalls (13), and a capacitor having an upper electrode (22) with sidewalls (23). A recess (41) is formed in the upper portion of the isolation trench (40), and the upper electrode (22) of the capacitor has a buried portion buried in the recess (41). The outer edge (E1) of the buried portion of the upper electrode (22) is located inside the outer edge (E2) of the sidewalls (23).
A semiconductor storage device comprising:
Dependencies are inferred from the claim text.