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US 2006/0125011 A1Published application
Memory with split gate devices and method of fabrication
AssigneeIntel Corporation
InventorPeter Chang
Life of this patent
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Abstract
A DRAM fabricated on an SOI substrate employing single body devices as memory cells without relying on a field through the insulative layer of the SOI is described. Floating body devices are defined by orthogonally disposed lines with both a front gate and back gate for each body being formed on the insulative layer.
Claims7
1-22. (canceled)
A memory comprising:
- an array of cells, the cells having first gate contacts, second gate contacts, source region contacts and drain region contacts;
- overlying metal bridges connected between pairs of the second gate contacts in an overlying metal layer;
- and
- additional contacts contacting the bridges and connecting them to lines in another overlying metal layer.
1 more element
A memory comprising:
- an array of cells, the cells having first gate contacts, second gate contacts, source region contacts and drain region contacts;
- and
- the second gate contacts being coupled to lines in a first layer of metalization, the source region contacts and first gate contacts being coupled to lines in a second layer of metalization and the drain region contacts being coupled to lines in a third layer of metalization.
Dependencies are inferred from the claim text.