Local ESD protection for low-capacitance applications

A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad against ESD events, said I/O pad located between a power pad and a ground potential pad, comprising:

• a first diode and a second diode connected in series, the anode of said first diode connected to said I/O pad and the cathode of said second diode connected to said power pad;
• a third diode with its anode connected to said ground pad and its cathode to said I/O pad;
• and
• an MOS transistor having a source connected to said ground pad, a gate connected to said ground pad, and a drain connected to said series between said first and said second diode, isolated from said I/O pad, said transistor positioned in close proximity and alignment with said second diode so that a localized parasitic silicon-controlled rectifier is formed, which is operable to distribute an ESD current.

A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad against ESD events, said I/O pad located between a power pad and a ground potential pad, comprising:

• a substrate of a first conductivity type;
• a first diode and a second diode connected in series, each diode in its own well of the opposite conductivity type in said substrate, the anode of said first diode connected to said I/O pad and the cathode of said second diode connected to said power pad;
• a third diode in said substrate with its anode connected to said ground pad and its cathode to said I/O pad;
• and
• a multi-finger MOS transistor in said substrate in close proximity to said well of said second diode, said MOS transistor comprising a source region, connected to said ground pad, a gate region, connected to said ground pad, and a drain region, connected to said series between said first and said second diode, isolated from said I/O pad;
• said second diode being interdigitated and having a plurality of anode regions of said first conductivity type, connected to the cathode of said first diode and to said drain, and a plurality of cathode regions of said opposite conductivity type, connected to said power pad;
• each transistor region aligned with a corresponding region of said second diode such that said diode-anode regions are positioned at a close proximity to said source regions, and said diode-cathode regions positioned at said close proximity to said drain regions;
• each of said transistor and second diode regions, respectively, coupled by said proximity and said connections, creating a localized parasitic silicon-controlled rectifier (SCR) comprising an SCR-anode formed by said diode-anode, a first base region formed by said second diode well, a second base region formed by said substrate, and an SCR-cathode formed by said transistor source, said SCR operable to distribute an ESD current.