Pattern evaluation method, manufacturing method of semiconductor device, correction method of mask pattern and manufacturing method of exposure mask

A manufacturing method of a semiconductor device comprising a pattern evaluation method using a circuit arrangement provided with N (N is a natural number of 2 or greater) circuit groups having wiring whose widths are different to each other, each circuit group including first to Mth circuits having first to Mth (M is a natural number of 2 or greater) wiring formed of a conductive layer, respectively, each of the first to the Mth wiring having the same width that is electrically measurable, the pattern evaluation method comprising:

• arranging patterns to be evaluated so that the Mth wiring or a layer in the vicinity thereof is locally removed;
• electrically calculating a first characteristic value indicating a characteristic of the first circuit including at least the wiring width of the first wiring;
• electrically calculating an Mth characteristic value which is a value indicating the characteristic of the Mth circuit and dependent on a geometric relationship between the pattern to be evaluated and the Mth wiring;
• and
• evaluating the characteristic of the pattern to be evaluated based on the first characteristic value to the Mth characteristic value obtained for at least two circuit groups of the N circuit groups.

A correction method of a mask pattern comprising evaluating a mask pattern using a circuit arrangement provided with N (N is a natural number of 2 or greater) circuit groups having wiring whose widths are different to each other, each circuit group including first to Mth circuits having first to Mth (M is a natural number of 2 or greater) wiring formed of a conductive layer, respectively, each of the first to the Mth wiring having the same width that is electrically measurable, and further comprising correcting the mask pattern on the basis of the evaluation result of the mask pattern, the evaluating the mask pattern including:

• arranging mask patterns to be evaluated so that the Mth wiring or a layer in the vicinity thereof is locally removed;
• electrically calculating a first characteristic value indicating a characteristic of the first circuit including at least the wiring width of the first wiring;
• electrically calculating an Mth characteristic value which is a value indicating the characteristic of the Mth circuit and dependent on a geometric relationship between the mask pattern to be evaluated and the Mth wiring;
• and
• evaluating the characteristic of the mask pattern to be evaluated based on the first characteristic value to the Mth characteristic value obtained for at least two circuit groups of the N circuit groups.

A manufacturing method of an exposure mask comprising a correction method of a mask pattern including evaluating a mask pattern using a circuit arrangement provided with N (N is a natural number of 2 or greater) circuit groups having wiring whose widths are different to each other, each circuit group including first to Mth circuits having first to Mth (M is a natural number of 2 or greater) wiring formed of a conductive layer, respectively, each of the first to the Mth wiring having the same width that is electrically measurable, and further including correcting the mask pattern on the basis of the evaluation result of the mask pattern, the evaluating the mask pattern having:

• arranging mask patterns to be evaluated so that the Mth wiring or a layer in the vicinity thereof is locally removed;
• electrically calculating a first characteristic value indicating a characteristic of the first circuit including at least the wiring width of the first wiring;
• electrically calculating an Mth characteristic value which is a value indicating the characteristic of the Mth circuit and dependent on a geometric relationship between the mask pattern to be evaluated and the Mth wiring;
• and
• evaluating the characteristic of the mask pattern to be evaluated based on the first characteristic value to the Mth characteristic value obtained for at least two circuit groups of the N circuit groups.