Methods for fabricating ferroelectric memory devices

A method for fabricating a ferroelectric memory device comprising the steps of:

• forming a lower insulation layer on a semiconductor substrate;
• forming ferroelectric capacitors in rows and columns on the lower insulation layer;
• forming conductive patterns, each electrically connected to a plurality of the ferroelectric capacitors that are adjacent along a row;
• forming an upper insulation layer on the semiconductor substrate, wherein the upper insulating layer includes via holes;
• and
• forming columns of plate lines, wherein each of the plate lines is electrically connected through the via holes in the upper insulation layer to the conductive patterns, and wherein at least two of the plate lines are on each of the conductive patterns.

A method for fabricating a ferroelectric memory device comprising the steps of:

• forming a lower insulation layer on a semiconductor substrate;
• forming a supporting insulation layer on the lower insulation layer;
• patterning the supporting insulation layer to form trenches arranged in rows and columns;
• forming bottom electrodes in the trenches on the supporting insulation layer;
• forming a ferroelectric layer on the bottom electrodes;
• forming an upper electrode layer on the ferroelectric layer;
• patterning the upper electrode layer to form upper electrodes arranged in rows and columns, and wherein each of the upper electrodes is on at least a row of four adjacent bottom electrodes;
• forming an upper insulation layer;
• and
• forming a plurality of columns of plate lines, wherein each of the plate lines is electrically connected to at least one of the upper electrodes through the upper insulation layer, and wherein at least two of the plate lines are on each of the upper electrodes.