Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and drain in CMOS technology

A transistor comprising:

• a gate structure formed over a substrate;
• sidewall spacers formed on the substrate adjacent the gate structure, the sidewall spacers including a low dielectric constant material encapsulated by one or more nitride materials;
• and
• source/drain regions formed within the substrate adjacent the gate structure, the sidewall spacers serving to guide dopants implanted into the substrate to form the source/drain regions into desired locations within the substrate.

A method of forming a transistor having a gate structure formed upon a substrate, comprising:

• forming a capping oxide layer over the gate structure and portions of the substrate adjacent the gate structure;
• forming a layer of material having a relatively low dielectric constant over the capping oxide layer;
• patterning the low dielectric constant material to form low dielectric constant sidewall spacers adjacent the gate structure;
• forming a layer of nitride material over the capping oxide layer and the low dielectric constant sidewall spacers;
• patterning the layer of nitride material so that the low dielectric constant sidewall spacers are encapsulated by nitride material;
• and
• doping portions of the substrate adjacent the gate structure to form source/drain regions therein, the sidewall spacers guiding dopant into select portions of the substrate.