Insulated gate type semiconductor device having a diffusion region contacting bottom and side portions of trenches
AssigneeKabushiki Kaisha Toshiba
InventorSatoshi Yanagisawa
Life of this patent
Estimating the term…
Loading patent…
AssigneeKabushiki Kaisha Toshiba
InventorSatoshi Yanagisawa
Estimating the term…
A surface region of a first base layer is formed with a second base layer. Trenches are formed over a range from the surface of the second base layer to the first base layer. The second base layer is divided into base layers. Each of first trenches is formed with a trench gate electrode. An emitter layer is formed in a surface region of the base layer intermittently selected from base layers positioned between first trenches, and contacts with the trench. Dummy trenches are formed over a range from the surface of the base region where the emitter layer is not formed to the first base layer at a position near to each of trenches. A diffusion region is formed in the first base layer to contact with the side portion of dummy trenches formed at the bottom of each trench and a position near thereto.
1-17. Canceled.
A method of manufacturing an insulated gate type semiconductor, comprising:
A method of manufacturing an insulated gate type semiconductor, comprising:
Dependencies are inferred from the claim text.