Nonvolatile semiconductor memory and manufacturing method for the same

A semiconductor memory having a memory cell site and a peripheral site disposed around the memory cell site, the semiconductor memory comprising:

• a memory cell matrix disposed in the memory cell site, including a plurality of cell columns arranged along a row-direction, each of cell columns is implemented by:
• a plurality of memory cell transistors serially connected along a column direction, each of the memory cell transistors having a first gate structure comprising a first cell site gate insulator, a first lower conductive layer disposed on the first cell site gate insulator, a first inter-electrode dielectric disposed on the first lower conductive layer, and a first upper conductive layer disposed on the first inter-electrode dielectric so that the first upper conductive layer is isolated from the first lower conductive layer by the first inter-electrode dielectric;
• and
• a select transistor arranged along the column-direction, configured to select the memory cell transistors arranged in the cell column, the select transistor having a second gate structure comprising a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer disposed on the second cell site gate insulator, a second inter-electrode dielectric disposed on the second lower conductive layer, and a second upper conductive layer disposed on the second inter-electrode dielectric so that the second upper conductive layer is conducted with the second lower conductive layer by an inter-electrode through-hole formed in the second inter-electrode dielectric;
• and
• peripheral circuitry disposed in the peripheral site, configured to drive the memory cell transistors and select transistors and to read information from the memory cell transistors, each of the peripheral circuitry is implemented by peripheral transistors, each of the peripheral transistors having a third gate structure comprising a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.