Polysilicon etch useful during the manufacture of a semiconductor device
AssigneeMicron Technology, Inc.
InventorDavid J. Keller
Life of this patent
Estimating the term…
Abstract
A method for etching a polysilicon layer comprises the steps of providing a semiconductor wafer substrate assembly having at least first and second features therein in spaced relation to each other which define an opening therebetween. A blanket polysilicon is formed over the wafer assembly and within the opening. A patterned photoresist layer is formed over the polysilicon layer, then the polysilicon layer within the opening is etched with a first etch. Subsequent to the first etch, the polysilicon with the opening is etched with a second etch comprising a halogen-containing gas flow rate of from about 35 sccm to about 65 sccm and an oxygen-containing gas (for example HeO2) flow rate of from about 12 sccm to about 15.6 sccm.
Claims7
A method used to etch a conductive layer to result in a selected profile of the conductive layer, comprising:
- providing a semiconductor wafer substrate assembly comprising a semiconductor wafer;
- forming a conductive layer over the semiconductor wafer, wherein the conductive layer comprises first and second vertically-oriented cross-sectional sidewalls, each sidewall comprising a lower portion and an upper portion continuous with the lower portion, with the upper portion being further away from the wafer than the lower portion;
- selecting a post-etch profile from first, second, and third post-etch profiles, wherein:
- the first post-etch profile results from an etch which removes lower and upper portions of each sidewall of the conductive layer at about the same rate to result in a substantially vertical profile of the conductive layer;
- the second post-etch profile results from an etch which removes the lower portion of each sidewall of the conductive layer at a faster rate than it removes the upper portion to result in a substantially U-shaped profile of the conductive layer;
- and
- the third post-etch profile results from an etch which removes the lower portion of each sidewall of the conductive layer at a faster rate than it removes the upper portion to result in the conductive layer having a profile which tapers inward at a uniform rate from the upper sidewall portion to the lower sidewall portion;
- and
- etching the conductive layer using an etch comprising a flow rate of between about 6 sccm and about 12 sccm HeO2,
- wherein the HeO2 flow rate is about 6 sccm to result in the conductive layer having the first profile;
- wherein the HeO2 flow rate is about 9 sccm to result in the conductive layer having the second profile;
- and
- wherein the HeO2 flow rate is about 12 sccm to result in the conductive layer having the third profile.
A method used during the formation of a semiconductor device, comprising:
- providing a semiconductor wafer substrate assembly comprising a semiconductor wafer;
- forming a blanket conductive layer over the semiconductor wafer;
- forming a silicide layer on the conductive layer;
- forming a dielectric layer on the silicide layer;
- etching the dielectric layer, the silicide layer, and the blanket conductive layer to form first and second sidewalls, each sidewall defined by the conductive layer, the silicide layer, and the dielectric layer, wherein a lower portion of the conductive layer is closer to the semiconductor wafer than an upper portion of the conductive layer;
- selecting a post-etch profile from first, second, and third post-etch profiles, wherein:
- the first post-etch profile results from an etch which removes lower and upper portions of the conductive layer at about the same rate to result in a substantially vertical profile of the conductive layer;
- the second post-etch profile results from an etch which removes the lower portion of the conductive layer at a faster rate than it removes the upper portion of the conductive layer to result in a substantially U-shaped profile of the conductive layer;
- and
- the third post-etch profile results from an etch which removes the lower portion of the conductive layer at a faster rate than it removes the upper portion of the conductive layer to result in the conductive layer having a profile which tapers inward at a uniform rate from the upper sidewall portion to the lower sidewall portion;
- and
- with the silicide layer on the conductive layer and the dielectric layer on the silicide layer, etching the conductive layer using an etch comprising a flow rate of between about 6 sccm and about 12 sccm HeO2,
- wherein the HeO2 flow rate is about 6 sccm to result in the conductive layer having the first profile;
- wherein the HeO2 flow rate is about 9 sccm to result in the conductive layer having the second profile;
- and
- wherein the HeO2 flow rate is about 12 sccm to result in the conductive layer having the third profile.
Dependencies are inferred from the claim text.