US 2004/0203205 A1 · Method of forming tiny silicon nitride spacer for flash EPROM by fully wet etching technology

Abstract

A method of forming very small silicon nitride spacers in split-gate flash EPROMs is disclosed which prevent the occurrence of “write disturb”, unwanted reverse tunneling, or erasing. This is accomplished by forming spacers with well-controlled dimensions and well-defined shapes through a judicious use of a fully wet etch technique, including main-etch and over-etch. The use of a phosphoric acid solution in combination with sulfuric acid+hydrogen peroxide widens the process window from a few seconds to several minutes so that the small-dimensioned silicon nitride spacers can be better controlled than it has been possible in the past. In the first embodiment phosphoric solution is used both for main-etch and for over-etch. In the second embodiment, phosphoric solution is used for main-etch only, while the sulfuric+hydrogen peroxide solution is used as an over-etch in forming the tiny silicon nitride spacers of the invention. In the third embodiment, the step of over-etching of the spacers is combined with the step of stripping off of an implant photomask, thus, shortening the manufacturing product cycle.

Claims28

Dependent claims

A method of forming tiny spacers for a flash EPROM cell, comprising the steps of:

providing a substrate having a plurality of active and field regions defined;
forming a gate oxide layer over said substrate;
forming a first polysilicon layer over said gate oxide layer;
etching said first polysilicon layer to define a floating gate structure;
forming a poly oxide layer over said first polysilicon layer;
forming a tunnel oxide layer over said substrate, including over said polyoxide layer;
forming a silicon nitride layer over said tunnel oxide layer;
performing a wet main-etch of said silicon nitride (SiN) layer to form first SiN spacers along the vertical sidewalls of said floating gate structure;
performing a wet over-etch of said first SiN spacers to form tiny second SiN spacers along the vertical sidewalls of said floating gate structure;
forming an intergate oxide layer over said floating gate;
forming a second polysilicon layer over said poly oxide layer;
and
etching said second polysilicon layer to form a control gate over said intergate poly oxide layer.

10 more elements

Dependencies are inferred from the claim text.

Method of forming tiny silicon nitride spacer for flash EPROM by fully wet etching technology

Life of this patent

Method of forming tiny silicon nitride spacer for flash EPROM by fully wet etching technology

Life of this patent

Abstract

Claims28