Ferroelectric capacitor memory device fabrication method

Abstract

A ferroelectric capacitor memory device is fabricated by forming a substrate including integrated circuitry with an interconnect layer and pass transistors. First capacitor electrodes are formed on the substrate and are connected to an associated pass transistor through the interconnect layer. A ferroelectric dielectric layer, formed on the first capacitor electrodes, is patterned to expose portions of the first capacitor electrodes to form a contact opening and a pad region. A second capacitor electrode is formed over the patterned ferroelectric layer to create a via within said contact opening, said via extending to said first capacitor electrode. A conductive layer is formed upon the second capacitor electrode. The conductive layer is patterned to form a plate line, said via connecting the first capacitor electrode to said plate line. The substrate forming step may be carried out so that the pass transistors comprise sources, drains and gates and the integrated circuitry comprises complementary metal oxide semiconductor (CMOS) circuitry comprising word lines, bit lines interconnect metal lines and contact plugs.

Dependencies are inferred from the claim text.