Contactless uniform-tunneling separate p-well (cusp) non-volatile memory array architecture, fabrication and operation

A method of setting a logic state of a memory cell, comprising:

• applying a first potential to a control gate of the memory cell, wherein the first potential has a first polarity;
• applying a second potential to a first source/drain region and a second source/drain region of the memory cell, wherein the second potential has a second polarity;
• applying the second potential to a first well containing the first and second source/drain regions;
• and
• applying a third potential to a second well underlying the first well, wherein the second well is coupled to the first well through a PN junction and wherein the third potential has the second polarity.

A method of setting a logic state of a memory cell in an array of memory cells, comprising:

• applying a first potential to a word line associated with the memory cell in a first column(s) of memory cells of a plurality of columns of memory cells, wherein the first potential has a first polarity;
• applying a second potential to a first source/drain region and a second source/drain region of the memory cell, wherein the second potential has a second polarity;
• applying the second potential to a first well of the first column, where the first well contains the first and second source/drain regions;
• applying a third potential to a first well of each of the remaining columns of memory cells of the plurality of columns;
• and
• applying a fourth potential to a second well, wherein the second well is underlying the first wells of the plurality of columns and is coupled to each of the first wells through a PN junction.

A method of setting a logic state of a memory cell in an array of memory cells, comprising:

• applying a first potential to a word line associated with the memory cell, wherein the memory cell is in a first column and the first potential has a first polarity;
• applying a second potential to a first source/drain region and a second source/drain region of the memory cell, wherein the second potential has a second polarity;
• applying the second potential to a first well of the first column, wherein the first well contains the first and second source/drain regions;
• applying a third potential to a first well of a second column;
• and
• applying a fourth potential to a second well underlying the first wells of the first and second columns, wherein the second well is coupled to the first wells through a PN junction and wherein the fourth potential has the second polarity.

A method of forming a column of non-volatile memory cells, comprising:

• forming two isolation trenches in a substrate;
• forming a first well between the isolation trenches, wherein the first well has a first conductivity type;
• forming a first source/drain region and a second source/drain region in the first well, wherein the first source/drain region is laterally separated from the second source/drain region to define an intermediate channel region and wherein the first and second source/drain regions have a second conductivity type different than the first conductivity type;
• forming a second well underlying and in contact with the isolation trenches, wherein the second well has the second conductivity type;
• forming a tunnel dielectric overlying at least the channel region;
• forming a floating gate overlying the tunnel dielectric;
• forming a control gate overlying the floating gate;
• and
• forming an interlayer dielectric between the floating gate and the control gate.

A method of forming a non-volatile memory cell, comprising:

• forming two isolation trenches in a substrate, wherein each isolation trench contains a dielectric material;
• conductively doping an exposed surface of the substrate to a first conductivity type between the isolation trenches, thereby forming a first well between the isolation trenches;
• conductively doping a first portion and a second portion of a surface of the first well to a second conductivity type opposite the first conductivity type, wherein the first portion of the first well is laterally separated from the second portion;
• conductively doping a portion of the substrate underlying and in contact with the isolation trenches to the second conductivity type;
• forming a first dielectric layer overlying a surface of the first well;
• forming a first conductive layer overlying the first dielectric layer, wherein the first conductive layer is capable of holding a charge;
• forming a second dielectric layer overlying the first conductive layer;
• and
• forming a second conductive layer overlying the second dielectric layer.