Semiconductor memory circuitry

(Currently amended) A semiconductor device including a memory, the semiconductor device comprising:

• a semiconductor die encapsulated in a package, the package having an encapsulating body and electrically conductive interconnect pins extending outwardly from the body;
• a total of from at least 16,000,000 to 17,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on the semiconductor die, the individual functional and operably addressable memory cells occupying area on the semiconductor die within the memory arrays, the occupied area of all functional and addressable memory cells on the semiconductor die having a total combined area which is no greater than 14 mm2;
• and
• peripheral circuitry and pitch circuitry formed on the semiconductor die relative to the memory arrays;
• the peripheral circuitry electrically interconnecting with the interconnect pins and including operably interconnected control and timing circuitry, address and redundancy circuitry, data and test path circuitry, and voltage supply circuitry which collectively enable full access to all addressable memory cells of the memory arrays.

(Withdrawn) A 4 M semiconductor memory device comprising:

• a semiconductor die encapsulated in a package, the package having an encapsulating body and electrically conductive interconnect pins extending outwardly from the body;
• a total of from 4,000,000 to 4,500,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on the die, the individual functional and operably addressable memory cells occupying area on the die within the memory arrays, the occupied area of all functional and addressable memory cells on the die having a total combined area which is no greater than 3.3 mm2;
• and
• peripheral circuitry and pitch circuitry formed on the die relative to the memory arrays;
• the peripheral circuitry electrically interconnecting with the pins and including operably interconnected control and timing circuitry, address and redundancy circuitry, data and test path circuitry, and voltage supply circuitry which collectively enable full access to all addressable memory cells of the memory arrays.

(Withdrawn) A 64 M semiconductor memory device comprising:

• a semiconductor die encapsulated in a package, the package having an encapsulating body and electrically conductive interconnect pins extending outwardly from the body;
• a total of from 64,000,000 to 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on the die, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells;
• and
• peripheral circuitry and pitch circuitry formed on the die relative to the memory arrays;
• the peripheral circuitry electrically interconnecting with the pins and including operably interconnected control and timing circuitry, address and redundancy circuitry, data and test path circuitry, and voltage supply circuitry which collectively enable full access to all addressable memory cells of the memory arrays.

(Currently amended) A semiconductor device including a memory, the semiconductor device comprising:

• a semiconductor die encapsulated in a package, the package having an encapsulating body and electrically conductive interconnect pins extending outwardly from the body;
• a total of from at least 16,000,000 to 17,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on the semiconductor die, at least one of the memory arrays containing at least one area of 100 square microns of continuous semiconductor die surface area having at least 128 of the functional and operably addressable memory cells;
• and
• peripheral circuitry and pitch circuitry formed on the semiconductor die relative to the memory arrays;
• the peripheral circuitry electrically interconnecting with the interconnect pins and including operably interconnected control and timing circuitry, address and redundancy circuitry, data and test path circuitry, and voltage supply circuitry which collectively enable full access to all addressable memory cells of the memory arrays.

(Withdrawn) A 4 M semiconductor memory device comprising:

• a semiconductor die encapsulated in a package, the package having an encapsulating body and electrically conductive interconnect pins extending outwardly from the body;
• a total of from 4,000,000 to 4,500,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on the die, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells;
• and
• peripheral circuitry and pitch circuitry formed on the die relative to the memory arrays;
• the peripheral circuitry electrically interconnecting with the pins and including operably interconnected control and timing circuitry, address and redundancy circuitry, data and test path circuitry, and voltage supply circuitry which collectively enable full access to all addressable memory cells of the memory arrays.