Method for forming gate segments for an integrated circuit

A method of forming a memory comprising:

• providing a processor;
• and
• coupling a memory device to the processor, the memory device formed by a method including:
• forming an array of memory cells interconnected with a plurality of bit lines and word lines, the word lines including sub-lithographic word lines, forming each cell includes forming an activation device with gates formed as gate segments that are separated by and self-aligned with a shallow trench isolation region;
• and
• coupling an addressing circuit to the array of memory cells to allow selective access to the memory cells, wherein forming the gate segments for the activation device includes depositing a conductive material and an insulating material after forming the shallow trench isolation region and before doping a source and drain.

A method of forming a memory comprising:

• providing a control circuit;
• and
• coupling a memory device to the control circuit, wherein the memory device is formed by a method including:
• forming an array of memory cells interconnected with a plurality of bit lines and word lines, forming each cell includes forming an activation device with gates formed as gate segments that are separated by and self-aligned with a shallow trench isolation region;
• coupling an addressing circuit to the array of memory cells to allow selective access to the memory cells, wherein forming each gate segment for the activation device includes:
• forming a shallow trench isolation region with a pad that extends outwardly from a layer of a semiconductor material;
• depositing a conductive material and an insulating material after forming the shallow trench isolation region and before doping a source and a drain region associated with the gate being formed;
• planarizing the conductive layer such that a working surface of the conductive layer is substantially coplanar with a surface of the shallow trench isolation region;
• and
• selectively removing portions of the conductive layer and the insulating layer to provide a region for forming the gate segment.

A method of forming a memory comprising

• forming a pair of memory cells for an integrated circuit using a lithographic process having a minimum lithographic dimension, wherein forming the pair of memory cells includes:
• forming two transistors in a semiconductor material, the transistors having a shared drain, each transistor having a gate and a source, the gate of each transistor formed as a gate segment that is separated by and self-aligned with a shallow trench isolation region, the gate of each transistor extending outwardly from the semiconductor material, wherein forming the gate segments for each transistor includes depositing a conductive material and an insulating material after forming the shallow trench isolation region and before doping a source and drain;
• forming two word lines outwardly from the transistors, wherein the word lines include sub-lithographic word lines with each word line having a width less than the minimum lithographic dimension, each word line connected to a gate of a different transistor, the word lines for activating the transistors;
• forming a bit line and two conductors outwardly from the transistors, the bit line coupled to the shared drain of the transistors, each conductor coupled to the source of a different transistor, the bit line and the two conductors adjacent to the word lines;
• and
• forming two storage capacitors outwardly from the bit line and the conductors, each storage capacitor coupled to a source of a different transistor by one of the conductors.

A method of forming a memory comprising:

• providing a microprocessor;
• and
• coupling a memory device to the microprocessor, wherein the memory device is formed by a method comprising:
• coupling a column decoder with input output circuitry to a plurality of bit lines and to a plurality of bit complement lines;
• coupling a row decoder to a plurality of word lines;
• coupling at least one address buffer to the row decoder and column decoder, wherein the address buffer receives an address of a selected cell and identifies a word line of the selected cell to the row decoder;
• coupling each sense amplifier of a plurality of sense amplifiers to a corresponding pair of bit line and bit complement line;
• and
• interconnecting an array of memory cells with the plurality of bit lines and word lines, the word lines including sub-lithographic word lines, wherein forming each cell includes forming an activation device with gates formed as gate segments that are separated by and self-aligned with a shallow trench isolation region, wherein forming the gate segments for the activation device includes depositing a conductive material and an insulating material after forming the shallow trench isolation region and before doping a source and drain.

A method of forming a memory comprising:

• providing a controller;
• and
• coupling a memory device to the controller, wherein the memory device is formed by a method comprising:
• coupling a column decoder with input output circuitry to a plurality of bit lines and to a plurality of bit complement lines;
• coupling a row decoder to a plurality of word lines;
• coupling at least one address buffer to the row decoder and column decoder, wherein the address buffer receives an address of a selected cell and identifies a word line of the selected cell to the row decoder;
• coupling each sense amplifier of a plurality of sense amplifiers to a corresponding pair of bit line and bit complement line;
• and
• interconnecting an array of memory cells with the plurality of bit lines and word lines, wherein forming each cell includes forming an activation device with gates formed as gate segments that are separated by and self-aligned with a shallow trench isolation region, wherein forming the gate segments for the activation device includes depositing a conductive material and an insulating material after forming the shallow trench isolation region and before doping a source and drain.