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US 2004/0061231 A1Published application
Interconnect structure for an integrated circuit and method of fabrication
AssigneeIntel Corporation
InventorsJun He, Jose Maiz, Hyun-Mog Park
Life of this patent
Estimating the term…
Abstract
An interconnect structure for an integrated circuit having several levels of conductors is disclosed. Dielectric pillars for mechanical support are formed between conductors in adjacent layers at locations that do not have vias. The pillars are particularly useful with low-k ILD or air dielectric.
Claims21
An interconnect structure for integrated circuit, comprising:
- a first plurality of spaced-apart, parallel conductors disposed at a first level above a substrate;
- a second plurality of spaced-apart, parallel conductors disposed at a second level above a substrate, the second conductors being disposed above the first conductors generally perpendicular to the first conductors, a projection of the second conductors on the first conductors defining a plurality of intersections;
- a plurality of vias providing a conductive path between selected ones of the first and second conductors at some of the intersections;
- a plurality of dielectric pillars extending between selected ones of the first and second conductors at other of the intersections for providing support for the second conductors from the first conductors.
1 more element
An interconnect structure for a integrated circuit comprising:
- a plurality of levels of conductors;
- a plurality of vias extending between selected conductors on adjacent levels;
- and
- a plurality of dielectric pillars, separate and distinct from a second dielectric disposed between the conductors, the pillars extending between conductors in adjacent layers where vias are not present.
1 more element
A method for providing an interconnect structure for an integrated circuit comprising:
- providing a plurality of levels of conductor, one above the other, each having a plurality of parallel, spaced-apart lines, the conductor in any one of the levels being perpendicular to the conductors in the level below it;
- providing vias between selected intersections of the lines in one of the levels and the lines in the level directly below it;
- and
- providing dielectric pillars at intersections of the lines in one level and the lines at the level below it, where such intersections do not have vias.
1 more element
A method comprising:
- forming a first dielectric layer on first conductors;
- forming first openings in the first dielectric layer;
- depositing a second dielectric layer on the first dielectric layer so as to fill the first openings;
- planarizing the second dielectric layer so as to expose the first dielectric layer and form pillars from the second dielectric layer;
- depositing a third dielectric layer on the first dielectric layer;
- defining via openings through the first and third dielectric layers exposing underlying first conductors;
- forming trenches above the via openings and pillars;
- and
- depositing a conductive material into the via openings and trenches.
6 more elements
A method comprising:
- forming a first dielectric layer on a plurality of spaced-apart first conductors;
- masking and etching the first dielectric layer so as to form pillars at predetermined locations on the conductors;
- forming a second dielectric layer over the pillars and conductors;
- opening vias and trenches in the second dielectric, including trenches disposed above the pillars;
- forming a barrier layer so as to line the via openings and trenches;
- depositing a conductive layer so as to fill the via openings and trenches;
- planarizing the surface of the conductive layer to form second conductors;
- and
- forming shunts over the second conductors.
6 more elements
Dependencies are inferred from the claim text.